# Scaled analog chip — findings and deliverables

## What "scaled" actually means here

Three things must scale together. Two do freely; one is bounded by 2D physics.

1. **Routing scales — proven.** `dn_router.py` is pure Python and the scale-free
   claim was checked directly: growing 1 → 256 cells (24 → 6144 nets), max
   dims/cell stays flat at 3. Layer count is a property of *local* cell density,
   not total cell count, because phyllotaxis keeps every cell fixed-density. This
   is the manufacturable sense of "infinitely scalable": adding cells never
   exhausts layers.

2. **Analog contract scales — inherited.** The φ-emergent Kuramoto substrate
   (`hdgl_analog_v30_reference.c`) is coupling-based and cell-count-agnostic;
   per-cell mismatch (σ≈0.035, ~4 effective bits) averages down as more cells
   couple. More coupled nodes = more effective bits. The lattice IS the
   mismatch-averaging vehicle.

3. **Board diameter is the real wall.** A monolithic Vogel spiral of cells grows
   as √N·C0 in radius — fundamental to any 2D layout of fixed-size cells. The
   proven-CLEAN 8-cell board is already 375 mm, at the ~400 mm single-panel fab
   ceiling. So a single bigger disk dead-ends near 8 cells.

## Two levers, both delivered

### Lever A — tighten the cell (push the monolith further)
The vacancy pass frees via room, which lets the cell geometry tighten (C1 2.75,
RP 0.5, gap 3.0). This gets **NCELL=12 onto one 370 mm board** — 50% more cells
per fabricable board. `phyllo_scaled_tight.py`, knobs `C1/RP/GAP/NCELL/NPART/NRING`.

Honest status at NCELL=12: **9 track crossings remain, all in cell 1** — the
innermost strand cell, where the PILOT/SUM tap risers cross internal nets near
the inward pole. This is the same tap-convergence issue seen at the v2 wall,
resurfacing at higher density. DMIN and ring-pitch tweaks don't clear it; it
needs the cell-1 risers routed on inner layers (a structural generator change).
**NCELL=8 remains the proven-CLEAN unit** (0 flags at JLCPCB 6-layer spec).

### Lever B — tile clean boards (scale past the wall)
`panel_stamp.py` stamps N byte-identical copies of the CLEAN board into one panel
`.kicad_pcb`, each translated to a grid or Vogel position, with per-board net
remapping (each board gets its own copy of every net; boards couple only via edge
connectors). Because each stamped board is already certified CLEAN, the panel
inherits cleanliness by construction.

**Verified end-to-end:** a 4-board panel (832 footprints, 766×766 mm) audits
**0 flags / 0 hard overlaps at JLCPCB 6-layer spec**, exports Gerbers with **zero
net-ID errors**, and is independently re-parsed by gerbonara (13 layers + drill).

## The honest physical ladder

    tier 0  cell   (24 parts)      Vogel inside a board
    tier 1  board  (8 cells CLEAN) Vogel inside a panel, 375 mm
    tier 2  panel  (K boards)      grid/Vogel-packed, one fab panel
    tier 3  rack   (M panels)      backplane / connectors

Each fabricated unit is bounded and fabricable; total cell count is unbounded via
rack count. √N diameter growth is real and unbeatable in 2D — the second bot's
wall-diagnosis was correct — so scaling is by *tiling bounded units*, not by
growing one disk.

## Files

- `phyllo_scaled.py`      — parametrized generator, env knobs + fab-limit guard
- `phyllo_scaled_tight.py`— tightened geometry (NCELL=12 fits; cell-1 risers open)
- `panel_stamp.py`        — **stamps real multi-board panels** (net-remap fixed)
- `phyllo_panel.py`       — manifest-level tiler (positions + inter-board net map)
- `scale_test.py`         — reproduces the bounded-layer proof
- `phyllo_n8.kicad_pcb`   — the proven-CLEAN 8-cell unit board
- `panel4.kicad_pcb`      — example 4-board panel, CLEAN
- `panel4_gerbers/`       — its exported Gerber + drill set (fab-ready)

## Recommendation (unchanged from the analysis, now with runs behind it)

Silicon is the scale path — `panel_stamp.py` gives fabricable multi-board panels
today. Tubes are the flagship few-node demo (area/power kills lattice averaging).
Motors are a separate φ-locked-controller spinoff, not a compute substrate. The
one experiment that still gates fab spend is the N-cell phyllotactic Monte-Carlo
(effective-bits vs N) on the analog side — that's the analog_chip8 sweep, not a
routing question.
