# Maxing out the analog chip — 2D density + 3D stacking

## What "max out fabrication" means, and where the limits actually are

There are two ceilings, and they trade off:

- **Copper limit (per board):** we're already at fab minimums — 0.15 mm→0.10 mm
  vias, 0.09 mm clearance. Cell size is NOT via-limited; it's limited by (a) the
  component package and (b) angular routing-lane congestion inside each cell.
- **Diameter limit (per panel):** a 2D Vogel spiral grows as √N, capped at the
  ~500 mm fab-panel edge.

## Lever 1 — shrink the cell (why they were big)

The cell diameter was dominated by 24 **SOT-23** pads on a Vogel spiral. SOT-23 is
a fat discrete package (~2.9×1.3 mm). Swapping to **0402 passives + SOT-323
transistors** and re-tuning shrank the cell substantially. Honest caveat: once the
0402 board is made *clean*, the routing **rings** (not the pads) become the
dominant term, and the binding constraint is **angular lane congestion**, not via
blocking — so the package swap gives ~2–3× nodes/board, not the naive 8×.

## Lever 2 — HDI blind/buried vias

Blind pad-vias (F.Cu → dim-layer only, 0.10 mm drill, micro-via where adjacent)
stop through-holes from blocking unused inner layers, letting rings pack a little
tighter. Modest gain (angular congestion still binds), but real and stacked on
Lever 1.

**2D result — CLEAN at JLCPCB 6-layer spec:**

| unit | cells | nodes | diameter |
|------|------:|------:|---------:|
| SOT-23, original | 8 | 192 | 375 mm |
| 0402, HDI, **2D max** | **23** | **552** | **492 mm** |

552 coupled φ-cells on one clean 492 mm fab panel — the 2D maximum.

## Lever 3 — 3D (the real density axis)

The current design routes in pseudo-3D (Dₙ ladder = copper layers) but all cells
sit on **one 2D substrate**. Z was untouched — and Z is the axis that beats √N,
because stacking adds nodes with **zero** diameter growth and **zero** per-layer
routing overhead.

`rigidflex_stack.py` folds K byte-identical copies of the clean 552-node board
into one **rigid-flex** part: rigid sections connected by flex bridges, folded to
stack at ~1.2 mm Z-pitch, with the PILOT/SUM/PROBE/X-chain coupling buses riding
the flex bridges to ±1 Z-neighbour. The Kuramoto lattice becomes genuinely 3D:
in-plane Vogel coupling **plus** vertical coupling.

**Nodes per volume is constant in K (√N penalty gone):**

| folds (K) | total nodes | volume | nodes/cm³ | stack height |
|----------:|------------:|-------:|----------:|-------------:|
| 4  |  2 208 |   913 cm³ | 2.42 | 5 mm |
| 8  |  4 416 | 1 825 cm³ | 2.42 | 10 mm |
| 16 |  8 832 | 3 650 cm³ | 2.42 | 19 mm |
| 32 | 17 664 | 7 300 cm³ | 2.42 | 38 mm |

**K=32 → 17 664 coupled φ-cells in one 492×492 mm × 38 mm rigid-flex part.**

Chosen approach (you said "max density"): **HDI board core + rigid-flex fold** —
this beats stacked-rigid-with-connectors ~9× on nodes/cm³ (connectors waste Z and
edge area; rigid-flex folds one continuous part at minimal pitch).

## Why this is the right maximum

- In-plane: 552 nodes is the clean 2D max at the fab-panel edge. Pushing further
  needs a smaller *transistor* package than SOT-323 (angular congestion, not vias,
  is the wall) or a different cell topology.
- In Z: unbounded in principle; bounded in practice by rigid-flex fold count and
  thermal/assembly limits, not by routing.
- Analog: more coupled nodes = more mismatch averaging = more effective bits. The
  3D lattice couples each cell to in-plane neighbours AND ±Z, which is strictly
  more coupling per node than any 2D layout — the best case for the averaging
  mechanism the substrate depends on.

## Files (scale_up/)

- `phyllo_hd.py` — HD generator, knobs `PKG` (SOT23/SOT323/0402/0201), `HDI`,
  `C1`, `RP`, `NCELL`, `FAB_LIMIT_MM`
- `hdi_max.kicad_pcb` + `hdi_max_gerbers/` — the clean 552-node 492 mm 2D-max board
- `rigidflex_stack.py` — folds K clean boards into a 3D rigid-flex stack
- `stack4.kicad_pcb` — example 4-layer fold-out fab panel (2208 nodes)
- `stack4.json` — the 3D coupling manifest (in-plane + ±Z adjacency)

## Honest open items

- The flat fold-out panel should be DRC'd **per rigid section**, not as one flat
  board (each section is the certified-clean unit; a whole-panel flat-DRC
  mis-flags folded sections against each other — not a real defect).
- Real rigid-flex needs a stackup spec (which layers are flex) from the chosen
  fab; the generator marks bridge regions but doesn't yet emit the flex stackup.
- Beyond ~552 nodes/board in-plane needs a smaller transistor package or a cell
  redesign — 0402/SOT-323 is near the angular-congestion wall.
