# 100 W desktop analog φ-accelerator — complete build

## The honest read on "100 W"

Discrete analog φ-cells are **low power** (~1 mW idle each). So 100 W is not a
cell-count target — it is a **system power envelope**, and the power is spent on
**precision**, not on more cells. Running each cell at higher bias current
(≈10 mA vs µA idle) lowers its noise floor and raises its effective resolution
from ~4–6 bits to **~8 bits**; that bias current is what consumes the 100 W.

Node count is therefore set by a sensible desktop board stack, not by the wattage.

## Unit board — fabricable now, Gerbers included

- **0402 passives + SOT-323 transistors, HDI blind/buried vias, 6-layer**
- **21 φ-cells = 504 analog nodes**, 473 mm diameter, 494 parts
- **CLEAN at JLCPCB 6-layer spec**: 0 clearance flags, 0 hard overlaps, 0 orphan
  nets, 0 net-ID export errors
- Gerbers re-verifiable with gerbonara; `unit100w_gerbers/` is fab-ready (35 files)

## 100 W system — 8-board stack

| quantity | value |
|----------|------:|
| boards | 8 |
| φ-cells | 168 |
| analog nodes | 4 032 |
| bias/cell | 10 mA (~8 effective bits) |
| throughput | ~0.032 TMAC/s |
| form | desktop tower, 473 mm dia × 120 mm tall |

**Power budget (100 W total):**

- cells (168 × 12 V × 10 mA): **20.2 W**
- drive / buffers / readout (8 × 0.5 W): **4.0 W**
- PSU losses + cooling (fans/pump): **75.8 W** headroom

100 W is comfortably cooled by forced air or a liquid gap between boards — this is
a desktop-class thermal load, not a datacenter one.

## Stack formula (scale to any budget)

    nodes  = boards × 504
    power  = cells × 12 V × I_bias  +  boards × 0.5 W drive  +  PSU/cooling
    bits   ≈ 4.5 + log2(I_bias / 100 µA)/… (higher bias → lower noise → more bits)

Run cells cooler (µA) for many boards at low power; run them hot (mA) for fewer
boards at higher precision. The 100 W build chooses the precision end.

## What it computes

A massively-parallel analog optimizer: coupled-oscillator equilibrium — Ising /
annealing / associative recall. **Not** a general CPU. At 100 W bias the ~8-bit
precision is its best operating point; the 4 032-node lattice couples each cell to
~6 in-plane neighbors (+ board-to-board via the stack connectors).

## Files
- `unit100w_gerbers/` + `.zip` — the fab-ready Gerber + drill set (35 files)
- `unit100w.kicad_pcb` — the clean board (KiCad 7)
- `unit100w_F_Cu.png` — top-copper render (21-cell phyllotactic spiral)
- `system100w_spec.json` — full machine-readable spec
