# 50–100 W fabricable 3D analog φ-computer — grounded, with vacuum + thermal

This is the return to grounded fabrication after the side-quests. It ships a
**real, orderable silicon system now**, and — the elegant part — the vacuum it
needs for thermal management is the *same* vacuum the roadmap's field-emission
tubes need, so the upgrade path is built in, not bolted on.

## Note on the attached "Unified Force" distillation

Treated as **speculative design-reference only** (the golden-ratio / Kuramoto
*structure* is real math; the physical claims — gravity-from-Schumann, anti-grav,
cloaking — are outside established science and are **not** imported into anything
fabricated here). Everything below is grounded in what ngspice and a real PCB fab
verify.

## Verified foundation (ngspice + Monte-Carlo, re-runnable)

- φ-cell settles to **1.618034** (exact).
- coupling averages device mismatch as **1/√N**: ~4 bits (N=1) → ~8.6 bits (N=1024).
- **cold stacks with averaging**: at 256 cells, 300 K → 77 K adds ~0.8 effective
  bits (7.8 → 8.6). This is why the thermal work matters — it directly buys precision.

## The final side-quest, resolved: vacuum + thermopile + cold

- **Vacuum, three real roles:** (a) field-emission micro-tubes *are* vacuum devices;
  (b) vacuum kills convection → holds a temperature gradient; (c) protects CNT tips.
- **Thermopile (Seebeck):** a Bi₂Te₃ junction stack across the core/shell gradient
  generates voltage. Direct self-bias *fails* (thermopile is low-V, the chip wants
  high-V) — but a **printed Cockcroft-Walton multiplier** bridges it (10 V → kV at
  nA). Honest: that self-bias chain is prototype-level, not shipping.
- **Cold buys bits:** Johnson noise ∝ √T. 77 K ≈ +1 bit, 4 K ≈ +3 bits, stacking
  with 1/√N. This is the grounded reason to cool.
- **kV / nA regime:** 30 kV × 100 nA = 3 mW — harmless power, maximally expressive
  field-emission nonlinearity (verified Fowler-Nordheim gain rises 3.6× from 10→30 kV).

## What SHIPS NOW (50–100 W, orderable)

- **unit board:** the CLEAN 21-cell 0402 HDI 6-layer board (Gerbers + BOM +
  positions included; 0 flags at JLCPCB spec, 0 net-ID export errors)
- **8-board vacuum-enclosed stack** → 168 cells / 4 032 nodes
- **Bi₂Te₃ thermopile** between warm core and cool shell (off-shelf TEC modules)
- **TEC/Peltier cold plate** on the shell (staged TEC; LN₂ option for 77 K)
- **silicon BJT gain cells** — the proven, ngspice-verified path
- power split (100 W): ~25 W cells+drive, ~45 W thermoelectric cooling, ~30 W
  PSU + vacuum pump

## Three design paths — all honored

| path | status here |
|------|-------------|
| **silicon / carbon / crystal** | **silicon SHIPS NOW** (cells + core reference); carbon-print & grown-quasicrystal bulk are documented roadmap |
| **tubes** | the vacuum enclosure is **built for the thermal job**, so CNT field-emission micro-tubes **drop in as an upgrade** — no redesign |
| **incandescent / motor** | realized as the **thermal tie-in**: the thermopile *is* the heat-to-work element; piezo transducers on the shell do readout |

## The keystone

**One vacuum enclosure serves two masters:** the thermal isolation that holds the
gradient (real cooling + precision now) *and* the environment field-emission tubes
require (the upgrade later). Nothing is wasted — building the fabricable thermal
system today is simultaneously building the socket for the tube/crystal future.

## Honest real-vs-roadmap line

- **Real now:** silicon cells; vacuum enclosure; Bi₂Te₃ thermopile; TEC cooling;
  the verified φ-settling, 1/√N averaging, and cold-precision gain.
- **Roadmap (not fab-ready):** CNT micro-tube gain; printed CW self-bias; grown
  quasicrystal bulk. Designed-for, not claimed-as-shipping.

## Files
- `unit_board_gerbers/` + `.zip` — CLEAN 6-layer Gerbers (orderable)
- `chip_unit.kicad_pcb` — the board (KiCad 7)
- `BOM.csv`, `positions.csv` — assembly
- `chip_5010w_spec.json` — full system spec (power, thermal, three paths, roadmap)
